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 74LVC1G66
Bilateral switch
Rev. 06 -- 27 August 2007 Product data sheet
1. General description
The 74LVC1G66 is a low-power, low-voltage Si-gate CMOS device. The 74LVC1G66 provides one single pole, single-throw analog switch function. It has two input/output terminals (Y and Z) and an active HIGH enable input pin (E). When E is LOW, the analog switch is turned off. Schmitt-trigger action at the enable input makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 1.65 V to 5.5 V.
2. Features
s Wide supply voltage range from 1.65 V to 5.5 V s Very low ON resistance: x 7.5 (typical) at VCC = 2.7 V x 6.5 (typical) at VCC = 3.3 V x 6 (typical) at VCC = 5 V s Switch current capability of 32 mA s High noise immunity s CMOS low power consumption s TTL interface compatibility at 3.3 V s Latch-up performance meets requirements of JESD78 Class I s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Enable input accepts voltages up to 5.5 V s Multiple package options s Specified from -40 C to +85 C and -40 C to +125 C
NXP Semiconductors
74LVC1G66
Bilateral switch
3. Ordering information
Table 1. Ordering information Package Temperature range Name 74LVC1G66GW 74LVC1G66GV 74LVC1G66GM 74LVC1G66GF -40 C to +125 C -40 C to +125 C -40 C to +125 C -40 C to +125 C TSSOP5 SC-74A XSON6 XSON6 Description plastic thin shrink small outline package; 5 leads; body width 1.25 mm plastic surface-mounted package; 5 leads plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm Version SOT353-1 SOT753 SOT886 SOT891 Type number
4. Marking
Table 2. Marking Marking code VL V66 VL VL Type number 74LVC1G66GW 74LVC1G66GV 74LVC1G66GM 74LVC1G66GF
5. Functional diagram
1 Z
001aag487
E Y
1 1 X1
mna076
2
4#
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Z
Y E
VCC
mna658
Fig 3. Logic diagram
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Product data sheet
Rev. 06 -- 27 August 2007
2 of 22
NXP Semiconductors
74LVC1G66
Bilateral switch
6. Pinning information
6.1 Pinning
74LVC1G66 74LVC1G66
Y Z 1 2 GND GND 3
001aad654
Y 5 VCC
1
6
VCC Y Z
74LVC1G66
1 2 3 6 5 4 VCC n.c. E
Z
2
5
n.c.
3
4
E
GND
4
E
001aag498
001aag499
Transparent top view
Transparent top view
Fig 4. Pin configuration SOT353-1 and SOT753
Fig 5. Pin configuration SOT886
Fig 6. Pin configuration SOT891
6.2 Pin description
Table 3. Symbol Y Z GND E n.c. VCC Pin description Pin SOT353-1/SOT753 1 2 3 4 5 SOT886/SOT891 1 2 3 4 5 6 independent input or output independent output or input ground (0 V) enable input (active HIGH) not connected supply voltage Description
7. Functional description
Table 4. Input E L H
[1] H = HIGH voltage level; L = LOW voltage level
Function table[1] Switch OFF-state ON-state
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Product data sheet
Rev. 06 -- 27 August 2007
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74LVC1G66
Bilateral switch
8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI IIK ISK VSW ISW ICC IGND Tstg Ptot
[1] [2] [3]
Parameter supply voltage input voltage input clamping current switch clamping current switch voltage switch current supply current ground current storage temperature total power dissipation
Conditions
[1]
Min -0.5 -0.5 -50 [2]
Max +6.5 +6.5 50 VCC + 0.5 50 100 +150 250
Unit V V mA mA V mA mA mA C mW
VI < -0.5 V or VI > VCC + 0.5 V VI < -0.5 V or VI > VCC + 0.5 V enable and disable mode VSW > -0.5 V or VSW < VCC + 0.5 V
-0.5 -100 -65
Tamb = -40 C to +125 C
[3]
-
The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6. Symbol VCC VI VSW Tamb t/V Recommended operating conditions Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V
[2] [2] [1]
Conditions
Min 1.65 0 0 -40 -
Typ -
Max 5.5 5.5 VCC +125 20 10
Unit V V V C ns/V ns/V
[1]
To avoid sinking GND current from terminal Z when switch current flows in terminal Y, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Y. In this case, there is no limit for the voltage drop across the switch. Applies to control signal levels.
[2]
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Product data sheet
Rev. 06 -- 27 August 2007
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NXP Semiconductors
74LVC1G66
Bilateral switch
10. Static characteristics
Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage Conditions VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V II IS(OFF) input leakage pin E; VI = 5.5 V or GND; current VCC = 0 V to 5.5 V OFF-state leakage current ON-state leakage current supply current additional supply current input capacitance OFF-state capacitance ON-state capacitance VI = VIH or VIL; VCC = 5.5 V; see Figure 7 VI = VIH or VIL; VCC = 5.5 V; see Figure 8 VI = 5.5 V or GND; VSW = GND or VCC; IO = 0 A; VCC = 1.65 V to 5.5 V pin E; VI = VCC - 0.6 V; VSW = GND or VCC; IO = 0 A; VCC = 5.5 V
[2]
-40 C to +85 C Min 0.65VCC 1.7 2.0 0.7VCC Typ[1] 0.1 0.1 Max 0.35VCC 0.7 0.8 0.3VCC 5 5
-40 C to +125 C Unit Min 0.65VCC 1.7 2.0 0.7VCC Max 0.7 0.8 100 200 V V V V V V A A
0.35VCC V
0.3VCC V
[2]
IS(ON)
[2]
-
0.1
5
-
200
A
ICC
[2]
-
0.1
10
-
200
A
ICC
[2]
-
5
500
-
5000
A
CI CS(OFF) CS(ON)
-
2.0 6.5 11
-
-
-
pF pF pF
[1] [2]
All typical values are measured at Tamb = 25 C. These typical values are measured at VCC = 3.3 V.
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Product data sheet
Rev. 06 -- 27 August 2007
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NXP Semiconductors
74LVC1G66
Bilateral switch
10.1 Test circuits
VCC VIL IS
VI
VCC VIH Z IS
VO VI
E Y GND
E Z GND Y
IS
VO
001aag488
001aag489
VI = VCC or GND and VO = GND or VCC.
VI = VCC or GND and VO = open circuit.
Fig 7. Test circuit for measuring OFF-state leakage current
Fig 8. Test circuit for measuring ON-state leakage current
10.2 ON resistance
Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15. Symbol RON(peak) Parameter ON resistance (peak) Conditions VI = GND to VCC; see Figure 9 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V RON(rail) ON resistance (rail) VI = GND; see Figure 9 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V VI = VCC; see Figure 9 ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V 10.4 7.6 7.0 6.1 4.9 30 20 18 15 10 45 30 27 23 15 8.2 7.1 6.9 6.5 5.8 18 16 14 12 10 27 24 21 18 15 34.0 12.0 10.4 7.8 6.2 130 30 25 20 15 195 45 38 30 23 -40 C to +85 C Min Typ[1] Max -40 C to +125 C Unit Min Max
74LVC1G66_6
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Product data sheet
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74LVC1G66
Bilateral switch
Table 8. ON resistance ...continued At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graphs see Figure 10 to Figure 15. Symbol RON(flat) Parameter ON resistance (flatness) Conditions VI = GND to VCC ISW = 4 mA; VCC = 1.65 V to 1.95 V ISW = 8 mA; VCC = 2.3 V to 2.7 V ISW = 12 mA; VCC = 2.7 V ISW = 24 mA; VCC = 3.0 V to 3.6 V ISW = 32 mA; VCC = 4.5 V to 5.5 V
[1] [2] Typical values are measured at Tamb = 25 C and nominal VCC. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature.
[2]
-40 C to +85 C Min Typ[1] 26.0 5.0 3.5 2.0 1.5 Max -
-40 C to +125 C Unit Min Max
10.3 ON resistance test circuit and graphs
40 RON () 30 VSW VCC VIH E Y GND Z 10
(4) VI ISW (5)
mna673
(1)
20
(2) (3)
0 0
001aag490
1
2
3
4 VI (V)
5
RON = VSW/ISW.
(1) VCC = 1.8 V. (2) VCC = 2.5 V. (3) VCC = 2.7 V. (4) VCC = 3.3 V. (5) VCC = 5.0 V.
Fig 9. Test circuit for measuring ON resistance
Fig 10. Typical ON resistance as a function of input voltage; Tamb = 25 C
74LVC1G66_6
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Product data sheet
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74LVC1G66
Bilateral switch
55 RON () 45
001aaa712
15 RON () 13
001aaa708
35
(4) (3) (2) (1)
11
(1) (2)
25
9
(3) (4)
15
7
5 0 0.4 0.8 1.2 1.6 VI (V) 2.0
5 0 0.5 1.0 1.5 2.0 VI (V) 2.5
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 11. ON resistance as a function of input voltage; VCC = 1.8 V
Fig 12. ON resistance as a function of input voltage; VCC = 2.5 V
13 RON () 11
001aaa709
10 RON () 8
001aaa710
(1)
(1) (2)
9
(2) (3)
6
(3)
7
(4) (4)
5 0 0.5 1.0 1.5 2.0 2.5 3.0 VI (V)
4 0 1 2 3 VI (V) 4
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 13. ON resistance as a function of input voltage; VCC = 2.7 V
Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V
74LVC1G66_6
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Product data sheet
Rev. 06 -- 27 August 2007
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NXP Semiconductors
74LVC1G66
Bilateral switch
7 RON () 6
001aaa711
5
(1) (2)
4
(3)
(4)
3 0 1 2 3 4 VI (V) 5
(1) Tamb = 125 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (4) Tamb = -40 C.
Fig 15. ON resistance as a function of input voltage; VCC = 5.0 V
11. Dynamic characteristics
Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter tpd Conditions
[2][3]
-40 C to +85 C Min Typ[1] Max
-40 C to +125 C Unit Min Max
propagation delay Y to Z or Z to Y; see Figure 16 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[4]
0.8 0.4 0.4 0.3 0.2 5.3 3.0 2.6 2.5 1.9
2.0 1.2 1.0 0.8 0.6 12 6.5 6.0 5.0 4.2
1.0 1.0 1.0 1.0 1.0
3.0 2.0 1.5 1.5 1.0 15.5 8.5 8.0 6.5 5.5
ns ns ns ns ns ns ns ns ns ns
ten
enable time
E to Y or Z; see Figure 17 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
1.0 1.0 1.0 1.0 1.0
74LVC1G66_6
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Product data sheet
Rev. 06 -- 27 August 2007
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NXP Semiconductors
74LVC1G66
Bilateral switch
Table 9. Dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter tdis disable time Conditions E to Y or Z; see Figure 17 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance CL = 50 pF; fi = 10 MHz; VI = GND to VCC VCC = 2.5 V VCC = 3.3 V VCC = 5.0 V
[1] [2] [3] [4] [5] [6] Typical values are measured at Tamb = 25 C and nominal VCC. tpd is the same as tPLH and tPHL propagation delay is the calculated RC time constant of the typical ON resistance of the switch and the specified capacitance when driven by an ideal voltage source (zero output impedance). ten is the same as tPZH and tPZL tdis is the same as tPLZ and tPHZ CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + {(CL + CS(ON))x VCC2 x fo} where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CS(ON) = maximum ON-state switch capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; {(CL + CS(ON)) x VCC2 x fo} = sum of the outputs.
[6] [5]
-40 C to +85 C Min 1.0 1.0 1.0 1.0 1.0 Typ[1] 4.2 2.4 3.6 3.4 2.5 Max 10 6.9 7.5 6.5 5.0
-40 C to +125 C Unit Min 1.0 1.0 1.0 1.0 1.0 Max 13 9.0 9.5 8.5 6.5 ns ns ns ns ns
-
9.8 12.0 17.3
-
-
-
pF pF pF
11.1 Waveforms and test circuit
VI Y or Z input GND t PLH VOH Z or Y output VOL
mna667
VM
t PHL
VM
Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 16. Input (Y or Z) to output (Z or Y) propagation delays
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Product data sheet
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74LVC1G66
Bilateral switch
VI E GND t PLZ VCC Y or Z output LOW-to-OFF OFF-to-LOW VOL t PHZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND switch enabled switch disabled switch enabled
mna668
VM
t PZL
VM VX t PZH
Y or Z
Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 17. Enable and disable times Table 10. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC Output VM 0.5VCC 0.5VCC 1.5 V 1.5 V 0.5VCC VX VOL + 0.15 V VOL + 0.15 V VOL + 0.3 V VOL + 0.3 V VOL + 0.3 V VY VOH - 0.15 V VOH - 0.15 V VOH - 0.3 V VOH - 0.3 V VOH - 0.3 V
Supply voltage
74LVC1G66_6
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 -- 27 August 2007
11 of 22
NXP Semiconductors
74LVC1G66
Bilateral switch
VEXT VCC VI VO DUT
RT CL RL RL
G
mna616
Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. VEXT = External voltage for measuring switching times.
Fig 18. Load circuit for switching times Table 11. VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL open open open open open tPZH, tPHZ GND GND GND GND GND tPZL, tPLZ 2VCC 2VCC 6V 6V 2VCC
Supply voltage
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol THD Parameter total harmonic distortion Conditions RL = 10 k; CL = 50 pF; fi = 1 kHz; see Figure 19 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 10 k; CL = 50 pF; fi = 10 kHz; see Figure 19 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V 0.068 0.009 0.008 0.006 % % % % 0.032 0.008 0.006 0.001 % % % % Min Typ Max Unit
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Product data sheet
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74LVC1G66
Bilateral switch
Table 12. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol f(-3dB) Parameter -3 dB frequency response Conditions RL = 600 ; CL = 50 pF; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 ; CL = 5 pF; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 ; CL = 10 pF; see Figure 20 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V iso isolation (OFF-state) RL = 600 ; CL = 50 pF; fi = 1 MHz; see Figure 21 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V RL = 50 ; CL = 5 pF; fi = 1 MHz; see Figure 21 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V Vct crosstalk voltage between digital input and switch; RL = 600 ; CL = 50 pF; fi = 1 MHz; tr = tf = 2 ns; see Figure 22 VCC = 1.65 V VCC = 2.3 V VCC = 3.0 V VCC = 4.5 V 69 87 156 302 mV mV mV mV -37 -37 -37 -37 dB dB dB dB -46 -46 -46 -46 dB dB dB dB 200 350 410 440 MHz MHz MHz MHz > 500 > 500 > 500 > 500 MHz MHz MHz MHz 135 145 150 155 MHz MHz MHz MHz Min Typ Max Unit
74LVC1G66_6
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 -- 27 August 2007
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NXP Semiconductors
74LVC1G66
Bilateral switch
Table 12. Additional dynamic characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 C. Symbol Qinj Parameter charge injection Conditions CL = 0.1 nF; Vgen = 0 V; Rgen = 0 ; fi = 1 MHz; RL = 1 M; see Figure 23 VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 4.5 V VCC = 5.5 V 3.3 4.1 5.0 6.4 7.5 pC pC pC pC pC Min Typ Max Unit
11.3 Test circuits
VCC VIH E Y/Z
600
0.5VCC
RL
Z/Y
10 pF
VO
CL
fi
D
001aag492
Test conditions: VCC = 1.65 V: Vi = 1.4 V (p-p). VCC = 2.3 V: Vi = 2 V (p-p). VCC = 3 V: Vi = 2.5 V (p-p). VCC = 4.5 V: Vi = 4 V (p-p).
Fig 19. Test circuit for measuring total harmonic distortion
VCC VIH
0.1 pF
0.5VCC
RL
E Y/Z Z/Y
VO
CL
fi
50
dB
001aag491
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads -3 dB.
Fig 20. Test circuit for measuring the frequency response when switch is in ON-state
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Product data sheet
Rev. 06 -- 27 August 2007
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74LVC1G66
Bilateral switch
0.5VCC
RL VIL 0.1 pF
VCC E Z/Y
0.5VCC
RL
Y/Z
VO
CL
fi
50
dB
001aag493
Adjust fi voltage to obtain 0 dBm level at input.
Fig 21. Test circuit for measuring isolation (OFF-state)
VCC E Y/Z G
logic input
Z/Y
VO
RL CL
50
600
0.5VCC
0.5VCC
001aag494
Fig 22. Test circuit for measuring crosstalk between digital input and switch
VCC E
Rgen
Y/Z
Z/Y
RL 1 M CL 0.1 nF
VO
G
logic input
Vgen
001aag495
logic input (E)
off
on
off
VO
VO
mna675
Qinj = VO x CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage.
Fig 23. Test circuit for measuring charge injection
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Product data sheet
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Bilateral switch
12. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1
D
E
A X
c y HE vMA
Z
5
4
A2 A1 (A3) A
1
e e1 bp
3
wM detail X
Lp L
0
1.5 scale
3 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.1 0 A2 1.0 0.8 A3 0.15 bp 0.30 0.15 c 0.25 0.08 D(1) 2.25 1.85 E(1) 1.35 1.15 e 0.65 e1 1.3 HE 2.25 2.0 L 0.425 Lp 0.46 0.21 v 0.3 w 0.1 y 0.1 Z(1) 0.60 0.15 7 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 REFERENCES IEC JEDEC MO-203 JEITA SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19
Fig 24. Package outline SOT353-1 (TSSOP5)
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Product data sheet
Rev. 06 -- 27 August 2007
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NXP Semiconductors
74LVC1G66
Bilateral switch
Plastic surface-mounted package; 5 leads
SOT753
D
B
E
A
X
y
HE
vMA
5
4
Q
A A1 c
1
2
3
detail X
Lp
e
bp
wM B
0
1 scale
2 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 1.1 0.9 A1 0.100 0.013 bp 0.40 0.25 c 0.26 0.10 D 3.1 2.7 E 1.7 1.3 e 0.95 HE 3.0 2.5 Lp 0.6 0.2 Q 0.33 0.23 v 0.2 w 0.2 y 0.1
OUTLINE VERSION SOT753
REFERENCES IEC JEDEC JEITA SC-74A
EUROPEAN PROJECTION
ISSUE DATE 02-04-16 06-03-16
Fig 25. Package outline SOT753 (SC-74A)
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Rev. 06 -- 27 August 2007
17 of 22
NXP Semiconductors
74LVC1G66
Bilateral switch
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm
SOT886
b 1 2 3 4x L1 L
(2)
e
6 e1
5 e1
4
6x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 1.5 1.4 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC MO-252 JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22
Fig 26. Package outline SOT886 (XSON6)
74LVC1G66_6 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 -- 27 August 2007
18 of 22
NXP Semiconductors
74LVC1G66
Bilateral switch
XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm
SOT891
1
2
b 3 4x
(1)
L1 e
L
6 e1
5 e1
4
6x
(1)
A
A1 D
E
terminal 1 index area 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 max 0.04 b 0.20 0.12 D 1.05 0.95 E 1.05 0.95 e 0.55 e1 0.35 L 0.35 0.27 L1 0.40 0.32 2 mm
Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION SOT891 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15
Fig 27. Package outline SOT891 (XSON6)
74LVC1G66_6 (c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 -- 27 August 2007
19 of 22
NXP Semiconductors
74LVC1G66
Bilateral switch
13. Abbreviations
Table 13. Acronym CMOS TTL HBM ESD MM DUT Abbreviations Description Complementary Metal Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic Discharge Machine Model Device Under Test
14. Revision history
Table 14. Revision history Release date 20070827 Data sheet status Product data sheet Change notice Supersedes 74LVC1G66_5 Document ID 74LVC1G66_6 Modifications: 74LVC1G66_5 Modifications:
*
Section 10 "Static characteristics": Changed: Conditions for OFF-state and ON-state leakage current. Product data sheet 74LVC1G66_4
20070807
* * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name when appropriate. Added type number 74LVC1G66GM (XSON6/SOT886 package) Added type number 74LVC1G66GF (XSON6/SOT891 package) Section 2 "Features": Added: Wide supply voltage range from 1.65 V to 5.5 V Changed: JESD78 Class II to JESD78 Class I Added: Enable input accepts voltages up to 5.5 V
* * *
Section 8 "Limiting values": Added: Limiting values of switch parameters. Added: Derating factors of the applicable packages Section 9 "Recommended operating conditions": Added: Recommended operation conditions of switch parameters. Section 10 "Static characteristics": Changed: Maximum values of ON resistance (peak) parameters and graphics. Changed: Conditions for input leakage and supply current.
*
74LVC1G66_4 74LVC1G66_3 74LVC1G66_2 74LVC1G66_1
Section 11 "Dynamic characteristics": Changed: Typical values of the charge injection. Product specification Product specification Product specification Product specification 74LVC1G66_3 74LVC1G66_2 74LVC1G66_1 -
20040413 20021115 20020529 20011030
74LVC1G66_6
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 -- 27 August 2007
20 of 22
NXP Semiconductors
74LVC1G66
Bilateral switch
15. Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
15.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
16. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
74LVC1G66_6
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 06 -- 27 August 2007
21 of 22
NXP Semiconductors
74LVC1G66
Bilateral switch
17. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms and test circuit . . . . . . . . . . . . . . . 10 Additional dynamic characteristics . . . . . . . . . 12 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 August 2007 Document identifier: 74LVC1G66_6


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